RELATED PATENT APPLICATIONS
Attorney's Docket Number TSMC97-125, "A Novel Method To Improve Flash EEPROM Write/Erase Threshold Closure," Ser. No.: 08/928,217, Filing Date: Sep. 12, 1997, assigned to the Same Assignee as the present invention.
Attorney's Docket Number TSMC97-126, "A Novel Method to Erase A Flash EEPROM Using Negative Gate Source Erase Followed By a High Negative Gate Erase," Ser. No.: 08/928,127, Filing Date: Sep. 12, 1997, assigned to the Same Assignee as the present invention.
Attorney's Docket Number TSMC97-085, "A Bi-Modal Erase Method For Eliminating Cycling-induced Flash EEPROM Cell Write/Erase Threshold Closure," Ser. No.: 08/927,472, Filing Date: Sep. 11, 1997, assigned to the Same Assignee as the present invention.
Attorney's Docket Number TSMC97-099, "A Novel Erase Method Of Flash EEPROM By Using Snapback Characteristic," Ser. No.: 08/957,678, Filing Date: Oct. 24, 1997, assigned to the Same Assignee as the present invention.
1. Field of the Invention
This invention relates generally to a class of non-volatile memory devices referred to as flash electrically erasable programmable read-only memory (flash EEPROM). More particularly, this invention relates to methods and means to erase digital data from a flash EEPROM cell and for eliminating trapped charges from the flash EEPROM cell.
2. Description of Related Art
The structure and application of the flash EEPROM is well known in the art. The Flash EEPROM provides the density advantages of an erasable programmable read-only memory (EPROM) that employs ultra-violet light to eliminate the programming with the speed of a standard EEPROM. FIG. 1a illustrates a cross-sectional view of a flash EEPROM cell of the prior art. The flash EEPROM cell 10 is formed within a p-type substrate 12. An n.sup.+ drain region 14 and an n.sup.+ source region 16 is formed within the p-type substrate 12.
A relatively thin gate dielectric 36 is deposited on the surface of the p-type substrate 12. The thin gate dielectric 36 will also be referred to as a tunneling oxide, hereinafter. A poly-crystalline silicon floating gate 32 is formed on the surface of the gate dielectric 36 above the channel region 34 between the drain region 14 and source region 16. An interpoly dielectric layer 30 is placed on the floating gate 32 to separate the floating gate 32 from a second layer of poly-crystalline silicon that forms a control gate 28.
A p.sup.+ diffusion 18 is placed in the p-type substrate 12 to provide a low resistance path from a terminal 20 to the p-type substrate. The terminal 20 will be attached to a substrate voltage generator Vsub. In most application of an EEPROM, the substrate voltage generator Vsub will be set to the ground reference potential (0 V).
The source region 16 will be connected to a source voltage generator VS through the terminal 22. The control gate 28 will be connected through the terminal 26 to the control gate voltage generator VG. And the drain region 14 will be connected through the terminal 24 to the drain voltage generator VD.
According to conventional operation, the flash EEPROM cell 10 is programmed by setting the gate control voltage generator VG to a relatively high voltage (on the order of 10 V). The drain voltage generator VD is set to a moderately high voltage (on the order of 5 V), while the source voltage generator VS is set to the ground reference potential (0 V).
With the voltages as described above, hot electrons will be produced in the channel 34 near the drain region 14. These hot electrons will have sufficient energy to be accelerated across the gate dielectric 36 and trapped on the floating gate 32. The trapped hot electrons will cause the threshold voltage of the field effect transistor (FET) that is formed by the flash EEPROM cell 10 to be increased by three to five volts. This change in threshold voltage by the trapped hot electrons causes the cell to be programmed.
During the programming process some of the hot electrons will be trapped 42 in the tunneling oxide 36 or in surface states 40 at the surface of the p-type substrate 12. These trapped electrons will cause the threshold voltage of the erased flash EEPROM cell 10 to increase.
To erase the flash EEPROM cell 10 as described in U.S. Pat. No. 5,481,494(Tang et al.), as shown in FIG. 2a, a moderately high positive voltage (on the order of 5 V) is generated by the source voltage generator VS. Concurrently, the gate control voltage generator VG is set to a relatively large negative voltage (on the order of -10 V). The substrate voltage generator VS are set to the ground reference potential. The drain voltage generator VD is usually disconnected from the terminal 24 to allow the drain region 14 to float. Under these conditions there is a large electric field developed across the tunneling oxide 36 in the source region 16. This field causes the electrons trapped in the floating gate 32 to flow to portion of the floating gate 32 that overlaps the source region 16. The electrons are then extracted to the source region 16 by the Fowler-Nordheim tunneling.
Further Tang et al. shows a method for tightening the threshold voltage VT distribution of an array of flash EEPROM cells. The moderately high positive voltage (5 V) that is applied to the source regions of the array of flash EEPROM cells and the relatively large negative voltage that is applied to the control gate insure a tighter distribution of the thresholds of the array of cells. The value of a load resistor between the low positive voltage and the source region is simultaneously reduced to a predetermined value so as to compensate for the increased erase time caused by the lowering of the magnitude of the negative constant voltage.
Referring back to FIG. 1a during the erasure process, some positive charges 38 will be forced and trapped in the tunneling oxide 36. These trapped positive charges 38 will cause the threshold voltage of the programmed flash EEPROM cell 10 to decrease. As can be shown in FIG. 3a, after repeatedly performing write/erase cycling, the combination of the decrease 52 in the programmed threshold voltage 50 and the increase 57 in the erased threshold voltage 55 will cause the separation of the programmed threshold voltage 50 and the erased threshold voltage 55 to close until the flash EEPROM cell 10 fails. At this time the flash EEPROM will no longer be able to operate reliably to store digital data.
Another illustration of the impact of the trapped charges is shown in FIG. 3b. FIG. 3b shows the drain current I.sub.d versus the voltage V.sub.g at the control gate for the cell of FIG. 1b. The set of curves 60 are for a cell that has been erased, while the set of curves 62 are for a cell that has been programmed. As can be seen, after 100K cycles of writing and erasing, the drain current I.sub.d will decrease for a given control gate voltage V.sub.g. Further FIG. 3b shows the change of transconductance G.sub.m versus the voltage V.sub.g at the control gate for the cell of FIG. 1b. The set of curves 64 are for a cell that has been erased and the set of curves 66 are for a cell that has been written. Again, as can been seen, having been exposed to 100k cycles of writing and erasing will cause the transconductance G.sub.m to shift for a given control gate voltage V.sub.g.
U.S. Pat. No. 5,485,423 (Tang et al.) as shown in FIG. 2b, describes a method of erasure of a flash EEPROM. A moderately large positive voltage pulse is generated by the source voltage generator VS. Simultaneously, a negative ramp voltage is developed by the gate control voltage generator VD. The drain voltage generator VG will be disconnected from the drain to allow the drain to float and the substrate voltage generator will be set to the ground reference potential as above described. This method will achieve an averaging of the tunneling field during the entire erase cycle.
U.S. Pat. No. 5,521,866 (Akaogi) and as shown in FIG. 1b describes non volatile semiconductor memory device having a floating gate 30. The memory device is constructed with a n-well 47 diffused into the semiconductor substrate 12 and a p-well 45 diffused into the n-well 47. The source 18 and drain 14 are then diffused into the p-well 45 with a floating gate 30 and control gate 28 disposed on the surface of the semiconductor substrate much as described in FIG. 1. The erasure process involves applying a positive voltage to p-well 45 and the n-well 47.
U.S. Pat. No. 5,596,528 (Kaya et al.) describes a method to program a flash EEPROM array will provide a narrow distribution of threshold voltage. The method eliminates the drain-column line loading effect and overcomes word line stress approach because high voltages are eliminated from the wordlines. The gate compaction is accomplished by reverse biasing the source and the substrate. This limits the channel currents in individual cells. If a cell loses its charge it will be restored by this method.